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S3C8478/c8475/p8475 product overview 1 - 1 1 product overview sam87rc product family samsung's new sam87rc family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. timer/counters with selectable operating modes are included to support real-time operations. many sam87rc microcontrollers have an external interface that provides access to external memory and other peripheral devices. a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum six cpu clocks) can be assigned to one interrupt level at a time. S3C8478/c8475 microcontroller the S3C8478/c8475 single-chip 8-bit microcontroller is designed for useful 10-bit resolution a/d converter, uart, pwm application field. its powerful sam87rc cpu architecture includes . the internal register file is logically expanded to increase the on-chip register space. the S3C8478/c8475 has 8/16 k bytes of on-chip program rom. following samsung's modular design approach, the following peripherals are integrated with the sam87rc core: ? large number of programmable i/o ports ( 42 sdip: 34 pins, 44 qfp: 36 pins ) ? one asynchronous uart module ? analog-to-digital converter with eight input channels and 10 -bit resolution ? one 8-bit basic timer for watchdog function ? one 8-bit timer/counter with three operating modes ( t imer 0) ? one general-purpose 16-bit timer/counters with three operating modes (timer 1) the S3C8478/c8475 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring complex timer/counter, pwm, capture, and uart. it is available in a 4 2 - pin sdip or 44-pin qfp package. otp the s3c8475 is an otp (one time programmable) version of the S3C8478/c8475 microcontroller. the s3c8475 microcontroller has an on-chip 16k-byte one-time-programmable eprom instead of a masked rom. the s3c8475 is comparable to the S3C8478/c8475, both in function in d.c. electrical characteristics and in pin configuration.
product overview S3C8478/c8475/p8475 1 - 2 features cpu ? sam87rc cpu core memory ? 272 -byte general purpose register area ? 8/16 k - byte internal program memory instruction set ? 79 instructions ? idle and stop instructions added for power-down modes instruction execution time ? 333 ns at 12 mhz f osc (minimum) interrupts ? 14 interrupt sources and 14 vectors ? eight interrupt levels ? fast interrupt processing general i/o ? five i/o ports (total 36 pins) ? four bit-programmable ports ? two n-channel open-drain output port timer/counters ? one 8-bit basic timer for watchdog function ? one 8-bit timer/counter with three operating modes (timer 0) ? one 16 - bit general-purpose timer/counters with three operation modes (timer 1) uart ? one uart module ? full duplex serial i/o interface with three uart modes a/d converter ? eight analog input pins ? 10 -bit conversion resolution ? 2 0 s conversion time ( 10 mhz cpu clock) buzzer frequency output ? 200 hz to 20 khz signal can be generated oscillator frequency ? 1 mhz to 12 mhz external crystal oscillator ? maximum 12 mhz cpu clock operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 1.8 v to 5.5 v package types ? 42 -pin sdip, 4 4-pin qfp
S3C8478/c8475/p8475 product overview 1 - 3 block diagram basic timer p1.3/buz p1.5/txd p1.4/rxd adc0-adc7 t1(cap) t1(pwm) t0(cap) t0(pwm) x out x in osc buz uart adc timer 1 timer 0 p1.0-p1.5 t0, t1ck, t1, buz, rxd, txd port 0 p0.0-p0.7 port i/o and interrupt control 8/16-kbyte rom 272-byte register file sam87rc cpu port 1 port 2 p2.0-p2.7 int0-int7 port 3 p3.0-p3.7 adc0-adc7 port 4 p4.0-p4.3 p4.4-p4.5 figure 1-1 . block diagram
product overview S3C8478/c8475/p8475 1 - 4 pin assignments p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 p4.3 p4.2 v dd v ss x out x in test p4.1 p4.0 reset p2.0/int0 p2.1/int1 p2.2/int2 S3C8478 s3c8475 42-sdip (top-view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p1.0/t0 (cap/pwm) p1.1/t1ck p1.2/t1 (cap/pwm) p1.3/buz p1.4/rxd p1.5/txd p3.7/adc7 p3.6/adc6 p3.5/adc5 p3.4/adc4 p3.3/adc3 p3.2/adc2 p3.1/adc1 p3.0/adc0 av ss av ref p2.7/int7 p2.6/int6 p2.5/int5 p2.4/int4 p2.3/int3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1-2 . pin assignment diagram ( 42 -pin sdip package)
S3C8478/c8475/p8475 product overview 1 - 5 p0.1 p0.0 p4.3 p4.2 v dd v ss x out x in test p4.1 p4.0 S3C8478 s3c8475 44-qfp (top-view) 1 2 3 4 5 6 7 8 9 10 11 p4.4 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p1.0/t0(cap/pwm) p1.1/t1ck p1.2/t1(cap/pwm) p1.3/buz 44 43 42 41 40 39 38 37 36 35 34 p1.4/rxd p1.5/txd p3.7/adc7 p3.6/adc6 p3.5/adc5 p3.4/adc4 p3.3/adc3 p3.2/adc2 p3.1/adc1 p3.0/adc0 av ss 33 32 31 30 29 28 27 26 25 24 23 reset p2.0/int0 p2.1/int1 p2.2/int2 p2.3/int3 p2.4/int4 p2.5/int5 p2.6/int6 p2.7/int7 p4.5 av ref 12 13 14 15 16 17 18 19 20 21 22 figure 1-3 . pin assignment diagram ( 4 4-pin qfp package)
product overview S3C8478/c8475/p8475 1 - 6 table 1- 1. S3C8478/c8475 pin descriptions pin name pin type pin description circuit number pin number share pins p0.0?p0.7 i/o nibble-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up resistors are assignable by software. e 8-1 (2-1, 43-38) ? p1.0?p1. 5 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are assignable by software. port 1 pin can also by used as alternative function (t0, t1ck, t1, buz, rxd, txd) d 42-37 (37-32) t0, t1ck, t1, buz, rxd, txd p2.0?p2. 7 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are assignable by software. port 2 pins can also be used as external interrupt. d 19-26 (13-20) int0- int7 p3.0?p3.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. pull-up resistors are assignable by software. port 3 pins can also be used as a/d converter by software. f 29-36 (24-31) adc0- adc7 p4.0?p4.3 i/o bit-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up resistors are assingable by software. e 17-16, 10-9 (11-10, 4-3) ? p4.4?p4.5 o push-pull output only c (44, 21) ? x in, x out ? crystal or ceramic oscillator signal for system clock. ? 14, 13 (8, 7) ? reset i system reset signal input pin. b 18 (12) ? test i test signal input pin (for factory use only; muse be connected to v ss ) ? 15 (9) ? av ref, av ss ? a/d converter reference voltage input and ground ? 27, 28 (22, 23) ? v dd, v ss ? voltage input pin and ground ? 11, 12 (5, 6) ? t0 i/o timer 0 capture input or pwm output pin d 42 (37) p1.0 t1ck i timer 1 external clock input pin d 41 (36) p1.1 t1 i/o timer 1 capture input or pwm output pin d 40 (35) p1.2 buz o 200hz-20khz frequency output for buzzer sound d 39 (34) p1.3 rxd i/o uart receive and transmit input or output d 38 (33) p1.4 txd o uart transmit output d 37 (32) p1.5 int0-int7 i external interrupt input e 19-26 (13-20) p2.0-p2.7 adc0- adc7 i a/d converter input f 29-36 (24-31) p3.0-p3.7 note : pin numbers shown in parentheses " ( ) " are for the 44 -pin qfp package.
S3C8478/c8475/p8475 product overview 1 - 7 pin circuit diagrams p-channel n-channel in v dd figure 1- 4. pin circuit type a schmitt trigger in v dd pull-up resistor figure 1-5 . pin circuit type b p-channel n-channel v dd out output disable data figure 1-6 . pin circuit type c output disable pull-up enable in/out circuit type c v dd data data figure 1-7 . pin circuit type d
product overview S3C8478/c8475/p8475 1 - 8 schmitt trigger n-ch v dd pull-up enable v dd in/out pne 47 k p-ch output disable data figure 1-8 . pin circuit type e output disable pull-up enable in/out circuit type c v dd data data to adc figure 1-9 . pin circuit type f
S3C8478/c8475/p8475 electrical data 14- 1 1 4 electrical data overview in this chapter , S3C8478/c8475 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? input/output capacitance ? d.c. electrical characteristics ? a.c. electrical characteristics ? oscillation characteristics ? oscillation stabilization time ? data retention supply voltage in stop mode ? uart timing characteristics in mode 0 ? a/d converter electrical characteristics
electrical data 14- 2 table 1. absolute maximum ratings a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all ports ? 0.3 to v dd + 0.3 v output voltage v o all output ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 1 , 2 , and 3 + 100 total pin current for ports 0 and 4 + 200 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c
S3C8478/c8475/p8475 electrical data 14- 3 table 14- 2. d.c. electrical characteristics (t a = - 40 c to + 85 c , v dd = 1.8 v to 5.5 v) parameter symbol test conditions min typ max unit input high voltage v ih1 ports 0, 1, 2, 3 ,4 and reset v dd = 2.7 to 5.5 v 0.8 v dd ? v dd v v ih3 x in, and x out v dd ?0.1 input low voltage v il1 ports 0, 1, 2, 3, 4 and reset v dd = 2.7 to 5.5 v ? ? 0.2 v dd v v il3 x in and x out 0.1 output high v oh i oh = ? 1 ma v dd = 4.5 to 5.5 v v dd ? 1.0 ? ? voltage ports 0, 1, 2, 3, 4 output low voltage v ol1 i ol = 15 ma v dd = 4.5 to 5.5 v ? 0.4 2.0 v port 0, and 4 v ol2 i ol = 4 ma v dd = 4.5 to 5.5 v 0.4 2.0 v ports 1, 2, and 3 input high leakage current i lih1 all input pins except i lih2 and reset v in = v dd ? ? 1 ua i lih2 x in, and x out v in = v dd 20 input low leakage current i lil1 all input pins except i lil2 v in = 0 v ? ? ? 1 ua i lil2 x in, and x out v in = 0 v ? 20 output high leakage current i loh all output pins v out = v dd ? ? 2 ua output low leakage current i lol all output pins v out = 0 v ? ? ? 2 ua pull-up resistor r p1 v in = 0 v, ports 0-4 v dd = 5 v 30 47 70 k w r p1 reset v dd = 5 v 100 200 350 supply current i dd1 rum mode 12 mhz cpu clock v dd = 4.5 to 5.5 v ? 10 20 ma 3 mhz cpu clock v dd = 1.8 to 2.2 v 1.1 3 i dd2 idle mode 12 mhz cpu clock v dd = 4.5 to 5.5 v ? 4 8 3 mhz cpu clock v dd = 1.8 to 2.2 v 0.6 1.5 i dd3 stop mode v dd = 4.5 to 5.5 v ? 0.1 5 ua v dd = 1.8 to 2.2 v 0.1 3
electrical data S3C8478/c8475/p8475 14- 4 table 14-3 . a.c. electrical characteristics (t a = - 40 c to + 85 c , v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl ports 2 v dd = 5 v 10 % ? 20 0 ? ns reset input low width t rsl input v dd = 5 v 10 % ? 1 ? m s t inth t intl 0.8 v dd 0.2 v dd t rst figure 14- 1. input timing measurement points
S3C8478/c8475/p8475 electrical data 14- 5 table 14-4 . oscillation characteristics (t a = ? 4 0 c + 85 c) oscillator clock circuit test condition min typ max unit main crystal or v dd = 4.5 v to 5.5 v 1 ? 12 mhz ceramic v dd = 2.7 v to 4.5 v 8 x in c1 c2 x out v dd = 1.8 v to 2.7 v 3 external clock v dd = 4.5 v to 5.5 v 1 ? 12 mhz (main system) v dd = 2.7 v to 4.5 v 8 x in x out v dd = 1.8 v to 2.7 v 3
electrical data S3C8478/c8475/p8475 14- 6 cpu clock 2 mhz main oscillator frequency (divided by 4) 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 4 mhz 6 mhz 8 mhz 10 mhz 12 mhz 1.8 v 2.7 v figure 14-2. operating voltage range table 14- 5. oscillation stabilization time (t a = ? 4 0 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator test condition min typ max unit main crystal f osc > 1.0 khz; ? ? 20 ms main ceramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator t wait when released by a reset (1) ? 2 1 6 /f osc ? ms stabilization wait time t wait when released by an interrupt (2) ? ? ? ms notes: 1. f osc is the oscillator frequency. 2. the duration of the oscillator stabilization wait time, t wait , when it is released by an interrupt is determined by the settings in the basic timer control register, btcon.
S3C8478/c8475/p8475 electrical data 14- 7 table 1 4-6 . uart timing characteristics in mode 0 (10 mhz) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v, load capacitance = 80 pf) parameter symbol min typ max unit serial port clock cycle time t sck 500 t cpu 6 700 ns output data setup to clock rising edge t s1 300 t cpu 5 ? clock rising edge to input data valid t s2 ? ? 300 output data hold after clock rising edge t h1 t cpu ? 50 t cpu ? input data hold after clock rising edge t h2 0 ? ? serial port clock high, low level width t high, t low 200 t cpu 3 400 notes : 1. all timings are in nanoseconds (ns) and assume a 10-mhz cpu clock frequency. 2. the unit t cpu means one cpu clock period. t high 0.8 v dd 0.2 v dd t low t sck figure 14-3 . waveform for uart timing characteristics
electrical data S3C8478/c8475/p8475 14- 8 note : the symbols shown in this diagram are defined as follows: t sck serial port clock cycle time t s1 output data setup to clock rising edge t s2 clock rising edge to input data valid t h1 output data hold after clock rising edge t h2 input data hold after clock rising edge data out d0 d1 d2 d3 d4 d5 d6 d7 t sck shift clock t s1 t h1 data in t s2 t h2 valid valid valid valid valid valid valid valid figure 14-4 . a.c. timing waveform for the uart module
S3C8478/c8475/p8475 electrical data 14- 9 table 14-7 . data retention supply voltage in stop mode (t a = ? 4 0 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 1.8 ? 5.5 v data retention supply current i dddr stop mode, v dddr = 1 . 8 v ? 0.1 5 a note : supply current does not include current drawn through internal pull-up resis tors or external output current loads. note: t wait is the same as 4096 x 16 x 1/f osc . execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilzation time data retention mode t wait reset v dd normal operating mode figure 14-5 . stop mode release timing w hen initiated by a reset a = 0.2 v dd b = 0.4 v dd c = 0.6 v dd d = 0.8 v dd v dd v out v ss v in a b c d figure 14-6 . schmitt trigger input characteristics
electrical data S3C8478/c8475/p8475 14- 10 table 14-8. a/d converter electrical characteristics (t a = ? 40 c to + 85 c , v dd = 2.7 v to 5.5 v, v ss = 0 v ) parameter symbol test conditions min typ max unit total accuracy ? v dd = 5.12 v ? ? 3 lsb integral linearity error ile cpu clock = 8 mhz av ref = 5.12 v ? 2 differential linearity error dle av ss = 0 v ? 1 offset error of top eot 1 3 offset error of bottom eob 1 2 conversion time (1) t con f osc = 10 mhz (3) 20 ? ? m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 ? ? m w adc reference voltage av ref ? 2.5 ? v dd v adc reference ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av cc = v cc = 5 v ? ? 10 m a analog block current (2) i adc av cc = v cc = 5 v ? 1 3 ma av cc = v cc = 3 v 0.5 1.5 av cc = v cc = 5 v power down mode 100 500 na notes: 1. "conversion time" is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion. 3. f osc is the main oscillator clock.
S3C8478/c8475/p8475 electrical data 14- 11 . . . . . 11 1111 1111 11 1111 1110 11 1111 1101 v (k-1) 00 0000 0010 00 0000 0001 00 0000 0000 av ss v eob v 2 v (k) v eot av ref analog input digital output 1lsb = (v eot -v eob )/1022 dle(k) = {(v (k) -v (k-1) )-1lsb}/1lsb ile(k) = {v (k) -(1lsb x k + v eob )}/1lsb dle = max{dle(k)} ile = max{ile(k)} figure 14-7. definition of dle and ile
S3C8478/c8475/p8475 mechanical data 15- 1 15 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram note : dimensions are in millimeters. 39.50 max 39.10 0 .2 0.50 0.1 1.778 (1.77) 0.51 min 3.30 0.3 3.50 0.2 5.08 max 42-sdip-600 0-15 1.00 0.1 0.25 + 0.1 - 0.05 15.24 14.00 0 .2 #42 #22 #21 #1 figure 15-1. 42-sdip-600 package dimensions
mechanical data S3C8478/c8475/p8475 15- 2 44-qfp-1010 #44 note : dimensions are in millimeters. 10.00 0.2 13.20 0.3 10.00 0.2 13.20 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 figure 15-2. 44-qfp-1010 package dimensions
S3C8478/c8475/p8475 s3p8475 otp 16- 1 16 s3p8475 otp overview the s3p8475 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C8478/c8475 microcontroller. it has an on-chip otp rom instead of a masked rom. the eprom is accessed by serial data format. the s3p8475 is fully compatible with the S3C8478/c8475, both in function in d.c. electrical characteristics and in pin configuration. because of its simple programming requirements, the s3p8475 is ideal as an evaluation chip for the S3C8478/c8475. p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 sdat /p4.3 sclk /p4.2 v dd /v dd v ss /v ss x out x in v pp /test p4.1 p4.0 reset reset / reset p2.0/ int0 p2.1/int1 p2.2/int2 s3p8475 (42-sdip) top-view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p1.0/t0(cap/pwm) p1.1/t1ck p1.2/t1(cap/pwm) p1.3/buz p1.4/rxd p1.5/txd p3.7/adc7 p3.6/adc6 p3.5/adc5 p3.4/adc4 p3.3/adc3 p3.2/adc2 p3.1/adc1 p3.0/adc0 av ss av ref p2.7/int7 p2.6/int6 p2.5/int5 p2.4/int4 p2.3/int3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the bolds indicate an otp pin name. figure 16-1. s3p8475 pin assignments (42-sdip package)
s3p8475 otp S3C8478 /c8475/p8475 16- 2 p0.1 p0.0 sdat /p4.3 sclk /p4.2 v dd /v dd v ss /v ss x out x in v pp /test p4.1 p4.0 s3p8475 (44-qf p ) top-view 1 2 3 4 5 6 7 8 9 10 11 p4.4 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p1.0/t0(cap/pwm) p1.1/t1ck p1.2/t1(cap/pwm) p1.3/buz 44 43 42 41 40 39 38 37 36 35 34 p1.4/rxd p1.5/txd p3.7/adc7 p3.6/adc6 p3.5/adc5 p3.4/adc4 p3.3/adc3 p3.2/adc2 p3.1/adc1 p3.0/adc0 av ss 33 32 31 30 29 28 27 26 25 24 23 reset reset / reset p2.0/int0 p2.1/int1 p2.2/int2 p2.3/int3 p2.4/int4 p2.5/int5 p2.6/int6 p2.7/int7 p4.5 av ref 12 13 14 15 16 17 18 19 20 21 22 note: the bolds indicate an otp pin name. figure 16-2. s3p8475 pin assignments (44-qfp package)
S3C8478/c8475/p8475 s3p8475 otp 16- 3 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p4.3 sdat 9(3) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p4.2 sclk 10(4) i serial clock pin. input only pin. test v pp 14(16) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is aplied, otp is in reading mode. (option) reset reset 18(12) i chip initialization v dd /v ss v dd /v ss 11(5)/12(6) ? logic power supply pin. v dd should be tied to +5 v during programming. note: ( ) means 44 qfp package. table 16-2. comparison of s3c8475 and S3C8478/c8475 features characteristic s3c8475 S3C8478/c8475 program memory 16-kbyte eprom 8/16-kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (ea) = 12.5 v pin configuration 42 sdip/44 qfp 42 sdip/44 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3c8475, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/ mem mem address (a15?a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.

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